Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 154

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.9
17.5.2.1
DS0200-003
DDCD, TERI, DDSR, and DCTS are cleared to ‘0’ when this register is read.
31:08
31:08
07:00
Offset 018h: UARTx_MSR – UART Modem Status Register
Offset 01Ch: UARTx_SPR – UART Scratch Pad Register
Bits
Bits
07
06
05
04
03
02
01
00
Type
Type
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
Reset
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
00h
0
0
Description
Reserved
Data Carrier Detect (DD): In normal mode, this bit reflects the inverted state of the
DCDx input pin. In loop back mode, this bit reflects the value of the UARTx_MCR.OUT2.
Ring Indicator (RI): In normal mode, this bit reflects the inverted state of the RIx
input pin. In loop back mode, this bit reflects the value of the UARTx_MCR.OUT1.
Data Set Ready (DSR): In normal mode, this bit reflects the inverted state of the
DSRx input pin. In loop back mode, this bit reflects the value of the UARTx_MCR.DTR.
Clear to Send (CTS): In normal mode, this bit reflects the inverted state of the CTSx
input pin. In loop back mode, this bit reflects the value of the UARTx_MCR.RTS.
Delta Status Change of DCD (DDCD): Set to ‘1’ when DCDx pin changes state.
Trailing Edge Change on RI (TERI): Set to ‘1’ when a falling edge is detected on
the RIx pin.
Delta Status Change of DSR (DDSR): Set when the DSRx pin changes state.
Delta Status Change of CTS (DCTS): Set when the CTSx pin changes state.
Description
Reserved
Scratchpad (SPR): Available for use as a general-purpose scratchpad register.
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