Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 119

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
14.5 Registers (Base → FFFF2000h)
14.5.1 Offset 000h: ADC_CFG – ADC Configuration Register
DS0200-003
31:29
28:26
25:23
22:20
19:17
16:14
13:11
10:08
07:00
Bits
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
Offset
00Ch
000h
004h
008h
010h
Reset
000
000
000
000
000
000
000
000
00h
Description
H-Channel Select (HCH_SEL):
G-Channel Select (GCH_SEL): Same encoding as HCH_SEL
F-Channel Select (FCH_SEL): Same encoding as HCH_SEL
E-Channel Select (ECH_SEL): Same encoding as HCH_SEL
D-Channel Select (DCH_SEL): Same encoding as HCH_SEL
C-Channel Select (CCH_SEL): Same encoding as HCH_SEL
B-Channel Select (BCH_SEL): Same encoding as HCH_SEL
A-Channel Select (ACH_SEL): Same encoding as HCH_SEL
ADC Clock Divider (ADC_CLK_DIV): Value used to derive the ADC clock from the
ADC hclk. This clock is driven into the analog section of the ADC and must be
configured to ensure that the divided clock is less than 600 kHz. The sample rate is
1/12 of the divided clock frequency.
 000: N/A
 001: ADC_IN[1] pin
 010: ADC_IN[2] pin
 011: ADC_IN[3] pin
 100: ADC_IN[4] pin
 101 - 111: N/A
 0: No clock to ADC (analog portion)
 1: ADC Divided Clock = hclk / 2
 2: ADC Divided Clock = hclk / 3
 ...
 255: ADC Divided Clock = hclk / 256
ADC_CMD
ADC_FIFO
Register
ADC_CFG
ADC_STA
ADC_INT
Description
ADC Configuration Register
ADC Command Register
ADC FIFO Register
ADC Interrupt Register
ADC Status Register
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