Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 33

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
5.6.4
DS0200-003
Before boot code begins searching external memory, it checks GPIO[0]. If this pin is high, boot code skips
external memory checks and tries to download an image from a UART.
If an image was not found in external memory, or if the download pin GPIO[0] was asserted, the boot code
tries to load an image from one of the UARTs. The boot code will search all of the UARTs for download
activity.
Since the operating frequency of the device is unknown, boot code uses the timers to perform automatic
baud rate detection. It expects the first character received to be the ASCII carriage return character ‘\r’ 013.
The timers will measure the length from the end of the start bit to the beginning of the stop bit to determine
the baud rate. The UART is setup using 8 data bits, no parity,1 stop bit. The maximum baud rate is limited
by the capability of the UART and system clock. A rate of 115k baud is achievable using a 24MHz clock.
Once the baud rate is setup, boot code displays a prompt as confirmation that the baud rate is setup
correctly. The boot code then expects an Intel hex file to be sent. This file is loaded at address 0. Once
download is complete (end of file record found), boot code executes the application at address 0.
A simple MMU table is implemented starting at address 00410000h. The Virtual to Physical mapping as well
as the Cacheable/Bufferable settings are shown below.
Boot Sequence
Boot ROM MMU Table
Download Pin (GPIO[0])
External Memory
UART Download




Bus Search: Boot code searches for code in external memory on nCS[0]. It searches the
secondary bus first followed by the primary bus.
Bus Width: Boot code initially sets up the memory controller for the maximum timings. The
boot code will first read the byte at offset 0 to determine the memory bus width. The boot code
programs this value into MEMC_CFG0.
Fixed Constant: Boot code then reads the data word at offset 0Ch for the fixed constant
D3C2B1A0h. If the boot code finds it, it reads the rest of the External Control Block (ECB)
parameters and sets up the memory controller timings and PLL based upon the ECB settings.
Starting Address: If the External Control Block was found, the boot code will then search for
the application start address immediately after the ECB. The application start address is the
first non-zero word following the ECB. Once the application start pointer is found, boot code
jumps to this application start address. Since ARM code must be word aligned, this address
must be word aligned. The CPU is placed in its reset state (the MMU and caches are disabled)
before branching to the start address.
Virtual Address
C0000000h
C0000000h
80000000h
00000000h
BFFFFFFFh
7FFFFFFFh
FFFFFFFFh
FFFFFFFFh
...
...
...
...
Physical Address
C0000000h
C0000000h
00000000h
00000000h
3FFFFFFFh
7FFFFFFFh
FFFFFFFFh
FFFFFFFFh
...
...
...
...
Cacheable/Bufferable
Cacheable & Bufferable
(write-back mode)
Non-Cacheable &
Non-Cacheable &
Non-Bufferable
Non-Bufferable
None
Non-cacheable view of
lowest quadrant.
APB Devices
Comments
Peripherals
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