Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 151

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.6
DS0200-003
31:08
02:00
Offset 00Ch: UARTx_LCR – UART Line Control Registers
Bits
07
06
05
04
03
Type
RW
RW
RW
RW
RW
RW
RO
Reset
000
0
0
0
0
0
0
Description
Reserved
Baud Rate Generator Access (DLAB):
UARTx_BRG_H is enabled.
Send Break (SB): When set, UART sends continuous zeroes on the transmit output
from the next bit boundary. Transmit data in the transmit shift register is ignored. After
writing this bit to ‘1’, TxD becomes ‘0’ after the bit boundary is reached. and the
transmit FIFO is cleared. Any new data written to the transmit FIFO during a break
must be written only after UARTx_LSR.THRE becomes ‘1’. New data is transmitted after
this bit is cleared for the next BRG edge.
Force Parity Error (FPE): When set, forces a parity error. When set and PEN is set,
an incorrect parity bit is transmitted with the data byte.
Even Parity Select (EPS): When cleared, uses odd parity for transmission. When
set, uses even parity for transmission. In multi-drop mode:
Parity Enable (PEN): When set, parity bit transmit and receive is enabled for every
character.
UART Character Parameter Selection (CHAR). See below.
UARTx_MCR.MDM
CHAR
0
0
1
1
000
001
010
011
100
101
110
111
Tx/Rx Data Bits
EPS
0
1
0
1
5
6
7
8
5
6
7
8
Even
Space
Parity Type
Odd
Mark. EPS resets to ‘0’ after the first character is
sent.
When set, access to UARTx_BRG_L and
Stop Bits (Tx Stop Bits)
1
1
1
1
2
2
2
2
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