Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 67

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
8.12 Registers (Base → FFFF4000h)
8.12.1 Global Registers
8.12.1.1
8.12.1.2
DS0200-003
31:17
15:08
07:00
31:08
07:00
Offset 000h: DMA_CTRL – DMA Control Register
Offset 004h: DMA_ISTAT – DMA Interrupt Status Register
Bits
Bits
16
Type
Type
RW
RW
RO
RO
RO
RO
Offset
000h
004h
Reset
Reset
00h
00h
0
0
0
0
Description
Reserved
External DMA Polarity (EXTPOL): Sets the polarity for ALL external DMA inputs and
outputs (TxREQ, TxACK, RxREQ, RxACK). When set, the polarity is active high.
Reserved
Channel “N” Interrupt Enable (IENx): When set, the interrupt for that channel is
enabled. Bit 7 = channel 7, bit 0 = channel 0.
Description
Reserved
Channel Interrupt Pending (PENDx): When set, an interrupt is pending for the
channel. More information in DMA_STAN, and all active bits of DMA_STAN must be
cleared for this bit to clear. These bits are set only DMA_CTRL.IENx is set.
DMA_ISTAT
DMA_CTRL
Register
Description
DMA Control Register
DMA Interrupt Status Register
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