Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 142

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.1.3 UART Modem Control
17.1.4 UART Interrupts
17.1.4.1
17.1.4.2
DS0200-003
The modem control logic provides two outputs and four inputs for handshaking with the modem. Any change
in the modem status inputs, except RI, is detected and an interrupt can be generated. For RI, an interrupt is
generated only when the trailing edge of the RI is detected. The module also provides LOOP mode for self-
diagnostics.
A Transmitter Hold Register Empty interrupt is generated if there is no data available in the transmit holding
register. A transmission complete interrupt is generated after the data in the shift register is sent. Both
interrupts can be independently disabled using individual interrupt enable bits, or cleared by writing data into
the UARTx_THR register.
A receiver interrupt can be generated by three possible sources. The first source, a receiver data ready,
indicates that one or more data bytes are received and are ready to be read. This interrupt is generated if
the number of bytes in the receiver FIFO is greater than or equal to the trigger level. If the FIFO is not
enabled, the interrupt is generated if the receive buffer contains a data byte. This interrupt is cleared by
reading the UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is generated when there
are fewer data bytes in the receiver FIFO than the trigger level and there are no READs and WRITEs to or
from the receiver FIFO for four consecutive byte times. When the receiver time-out interrupt is generated, it
is cleared only after emptying the entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an interrupt enable bit.
The third source of a receiver interrupt is a line status error, indicating an error in byte reception. This error
can result from one of the below conditions:
An interrupt (due to one of the above) is cleared when the UARTx_LSR register is read.
A line status interrupt is activated (provided this interrupt is enabled) differently depending on whether the
FIFO and DMA are enabled or not.
If the FIFO and DMA are not enabled, a line status interrupt from parity error, framing error or break
condition is generated immediately when the character is received. The over run error occurs after a second
character is received before the first has been read from the UARTx_RBR.
If the FIFO is enabled and DMA is not enabled the line status interrupt is activated when the READ pointer
of the receiver FIFO points to the location of the FIFO that contains a byte with an error (parity, framing or
break condition). The line status interrupt is activated due to an over run condition when the FIFO is full and
another character is received.
The receive character which causes the overrun condition is not written into the FIFO. The interrupt is
immediately cleared when the UARTx_LSR register is read. The ERR bit of the UARTx_LSR register is
active as long as an erroneous byte due to parity, framing or break condition is present anywhere in the
receiver FIFO.
If the FIFO and DMA are enabled, the line status interrupt is activated and the receive DMA request is
deactivated when a byte with a parity, framing or break detect error enters the ‘trigger level’ portion of the
receive FIFO. The line status interrupt will remain asserted while software alternately reads the UARTx_LSR
and UARTx_RBR until the location with the error has been removed from the FIFO.
For multi-drop mode, incorrect parity indicates detection of an address byte.
Transmitter Interrupt
Receiver Interrupts




Incorrect received parity
Incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte
Receiver over run condition
A BREAK condition being detected on the receive data input
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