MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 112

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resets and Interrupts
5.3.5 System Configuration Options Register
Technical Data
112
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
Address:
Special considerations are needed when a STOP instruction is executed
and the clock monitor is enabled. Because the STOP function causes
the clocks to be halted, the clock monitor function generates a reset
sequence if it is enabled at the time the stop mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register
to 0 to disable the clock monitor. After recovery from STOP, set the CME
bit to logic 1 to enable the clock monitor. Alternatively, executing a STOP
instruction with the CME bit set to logic 1 can be used as a software
initiated reset.
ADPU — Analog-to-Digital Converter Power-Up Bit
CSEL — Clock Select Bit
IRQE — Configure IRQ for Edge-Sensitive-Only Operation Bit
DLY — Enable Oscillator Startup Delay Bit
Reset:
Read:
Write:
Figure 5-2. System Configuration Options Register (OPTION)
Refer to
Refer to
Refer to
Section 10. Analog-to-Digital (A/D)
0 = IRQ is configured for level-sensitive operation.
1 = IRQ is configured for edge-sensitive-only operation.
$1039
ADPU
Bit 7
0
Section 10. Analog-to-Digital (A/D)
Section 10. Analog-to-Digital (A/D)
Section 4. Operating Modes and On-Chip Memory
Resets and Interrupts
= Unimplemented
CSEL
6
0
IRQE
5
0
(1)
DLY
4
1
(1)
Converter.
CME
3
0
M68HC11E Family — Rev. 3.2
Converter.
Converter.
2
0
CR1
1
0
(1)
MOTOROLA
CR0
and
Bit 0
0
(1)