MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 282

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Note
Boot ROM Firmware
282
RBOOT is reset to 1 in bootstrap mode to enable the small boot ROM.
In the other three modes, RBOOT is reset to 0 to keep the boot ROM out
of the memory map. While in special test mode, SMOD = 1, which allows
the RBOOT control bit to be written to 1 by software to enable the boot
ROM for testing purposes.
The main program in the boot ROM is the bootloader, which is
automatically executed as a result of resetting the MCU in bootstrap
mode. Some newer versions of the M68HC11 Family have additional
utility programs that can be called from a downloaded program. One
utility is available to program EPROM or OTP versions of the M68HC11.
A second utility allows the contents of memory locations to be uploaded
to a host computer. In the MC68HC711K4 boot ROM, a section of code
is used by Motorola for stress testing the on-chip EEPROM. These test
and utility programs are similar to self-test ROM programs in other
MCUs except that the boot ROM does not use valuable space in the
normal memory map.
Bootstrap firmware is also involved in an optional EEPROM security
function on some versions of the M68HC11. This EEPROM security
feature prevents a software pirate from seeing what is in the on-chip
EEPROM. The secured state is invoked by programming the no security
(NOSEC) EEPROM bit in the CONFIG register. Once this NOSEC bit is
programmed to 0, the MCU will ignore the mode A pin and always come
out of reset in normal single-chip mode or special bootstrap mode,
depending on the state of the mode B pin. Normal single-chip mode is
the usual way a secured part would be used. Special bootstrap mode is
used to disengage the security function (only after the contents of
EEPROM and RAM have been erased). Refer to the M68HC11
Reference Manual, Motorola document order number M68HC11RM/AD,
for additional information on the security mode and complete listings of
the boot ROMs that support the EEPROM security functions.
AN1060 — Rev. 1.0
MOTOROLA