MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 99

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.6.1.1 Block Protect Register
M68HC11E Family — Rev. 3.2
MOTOROLA
used; when CSEL is 1, an on-chip resistor-capacitor (RC) oscillator is
used.
The EEPROM programming voltage power supply voltage to the
EEPROM array is not enabled until there has been a write to PPROG
with EELAT set and PGM cleared. This must be followed by a write to a
valid EEPROM location or to the CONFIG address, and then a write to
PPROG with both the EELAT and EPGM bits set. Any attempt to set
both EELAT and EPGM during the same write operation results in
neither bit being set.
This register prevents inadvertent writes to both the CONFIG register
and EEPROM. The active bits in this register are initialized to 1 out of
reset and can be cleared only during the first 64 E-clock cycles after
reset in the normal modes. When these bits are cleared, the associated
EEPROM section and the CONFIG register can be programmed or
erased. EEPROM is only visible if the EEON bit in the CONFIG register
is set. The bits in the BPROT register can be written to 1 at any time to
protect EEPROM and the CONFIG register. In test or bootstrap modes,
write protection is inhibited and BPROT can be written repeatedly.
Address ranges for protected areas of EEPROM differ significantly for
the MC68HC811E2. Refer to
Bits [7:5] — Unimplemented
Address:
Reset:
Read:
Write:
Always read 0
Operating Modes and On-Chip Memory
$1035
Bit 7
0
Figure 4-16. Block Protect Register (BPROT)
= Unimplemented
6
0
5
0
Figure
PTCON
4
1
4-16.
Operating Modes and On-Chip Memory
BPRT3
3
1
BPRT2
2
1
BPRT1
Technical Data
1
1
EEPROM
BPRT0
Bit 0
1
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