MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 174

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Serial Peripheral Interface (SPI)
Technical Data
174
SPR[1:0]
0 0
0 1
1 0
1 1
E Clock By
Divide
16
32
2
4
E = 1 MHz (Baud)
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR[1:0] — SPI Clock Rate Select Bits
Frequency at
When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device has a steady state low
value. When CPOL is set, SCK idles high. Refer to
8.5 Clock Phase and Polarity
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPHA bit
selects one of two different clocking protocols. Refer to
and
These two bits select the SPI clock (SCK) rate when the device is
configured as master. When the device is configured as slave, these
bits have no effect. Refer to
62.5 kHz
31.3 kHz
500 kHz
250 kHz
8.5 Clock Phase and Polarity
Table 8-1. SPI Clock Rates
Serial Peripheral Interface (SPI)
E = 2 MHz (Baud)
Frequency at
62.5 kHz
1.0 MHz
500 kHz
125 kHz
Table
Controls.
E = 3 MHz (Baud)
8-1.
Frequency at
Controls.
187.5 kHz
93.8 kHz
1.5 MHz
750 kHz
M68HC11E Family — Rev. 3.2
Figure 8-2
E = 4 MHz (Baud)
Frequency at
Figure 8-2
250 kHz
125 kHz
2 MHz
1 MHz
MOTOROLA
and

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