MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 153

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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7.8.2 Serial Communications Control Register 1
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
The SCCR1 register provides the control bits that determine word length
and select the method used for the wakeup feature.
R8 — Receive Data Bit 8
T8 — Transmit Data Bit 8
Bit 5 — Unimplemented
M — Mode Bit (select character format)
WAKE — Wakeup by Address Mark/Idle Bit
Bits [2:0] — Unimplemented
Figure 7-4. Serial Communications Control Register 1 (SCCR1)
Reset:
Read:
Write:
If M bit is set, R8 stores the ninth bit in the receive data character.
If M bit is set, T8 stores the ninth bit in the transmit data character.
Always reads 0
Always read 0
1 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
I = Indeterminate after reset
Serial Communications Interface (SCI)
$102C
Bit 7
R8
I
= Unimplemented
T8
6
I
5
0
M
4
0
Serial Communications Interface (SCI)
WAKE
3
0
2
0
1
0
Technical Data
SCI Registers
Bit 0
0
153

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