EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 296
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Contents
Section II. Memory
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices
iv
Conclusion ............................................................................................................................................ 1–56
Revision History ..................................................................................................................... Section II–1
Introduction ............................................................................................................................................ 2–1
TriMatrix Memory ................................................................................................................................. 2–1
Using TriMatrix Memory ..................................................................................................................... 2–7
Clock Modes ......................................................................................................................................... 2–16
Designing With TriMatrix Memory .................................................................................................. 2–23
Read-During-Write Operation at the Same Address ..................................................................... 2–25
Conclusion ............................................................................................................................................ 2–27
Introduction ............................................................................................................................................ 3–1
External Memory Standards ................................................................................................................ 3–1
DDR Memory Support Overview ..................................................................................................... 3–10
VCCG & GNDG .............................................................................................................................. 1–52
External Clock Output Power ...................................................................................................... 1–53
Guidelines ........................................................................................................................................ 1–56
Clear Signals ...................................................................................................................................... 2–3
Parity Bit Support ............................................................................................................................. 2–3
Byte Enable Support ........................................................................................................................ 2–4
Implementing Single-Port Mode .................................................................................................... 2–7
Implementing Simple Dual-Port Mode ......................................................................................... 2–8
Implementing True Dual-Port Mode .......................................................................................... 2–11
Implementing Shift-Register Mode ............................................................................................. 2–14
Implementing ROM Mode ............................................................................................................ 2–15
Implementing FIFO Buffers .......................................................................................................... 2–16
Independent Clock Mode .............................................................................................................. 2–16
Input/Output Clock Mode ........................................................................................................... 2–18
Read/Write Clock Mode ............................................................................................................... 2–21
Single-Port Mode ............................................................................................................................ 2–23
Selecting TriMatrix Memory Blocks ............................................................................................ 2–24
Pipeline & Flow-Through Modes ................................................................................................ 2–24
Power-up Conditions & Memory Initialization ......................................................................... 2–25
Same-Port Read-During-Write Mode .......................................................................................... 2–25
Mixed-Port Read-During-Write Mode ........................................................................................ 2–26
DDR SDRAM .................................................................................................................................... 3–1
RLDRAM II ....................................................................................................................................... 3–4
QDR & QDRII SRAM ...................................................................................................................... 3–6
ZBT SRAM ......................................................................................................................................... 3–8
DDR Memory Interface Pins ......................................................................................................... 3–11
DQS Phase-Shift Circuitry ............................................................................................................ 3–15
Stratix Device Handbook, Volume 2
Altera Corporation
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