EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 460

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

I/O Pad Placement Guidelines
4–32
Stratix Device Handbook, Volume 2
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA
Table 4–8. Input-Only Bidirectional Pin Limitation Formulas
Package Type
Bidirectional Pins
Bidirectional pads must satisfy input and output guidelines
simultaneously. If the bidirectional pads are all controlled by the same OE
and there are no other outputs or voltage referenced inputs in the bank,
then there is no case where there is a voltage referenced input active at the
same time as an output. Therefore, the output limitation does not apply.
However, since the bidirectional pads are linked to the same OE, the
bidirectional pads act as inputs at the same time. Therefore, the input
limitation of 40 input pads (20 on each side of the VREF pad) applies.
If any of the bidirectional pads are controlled by different output enables
(OE) and there are no other outputs or voltage referenced inputs in the
bank, then there may be a case where one group of bidirectional pads is
acting as inputs while another group is acting as outputs. In such cases,
apply the formulas shown in
Consider a thermally enhanced FineLine BGA package with eight
bidirectional pads controlled by OE1, eight bidirectional pads controlled
by OE2, and six bidirectional pads controlled by OE3. While this totals 22
bidirectional pads, it is safely allowable because there would be a
maximum of 16 outputs per VREF pad possible assuming the worst case
where OE1 and OE2 are active and OE3 is inactive. This is particularly
relevant in DDR SDRAM applications.
When at least one additional voltage referenced input and no other
outputs exist in the same VREF bank, then the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> 40 (20 on
each side of the VREF pad)
<Total number of bidirectional pads> – <Total number of pads from the
smallest group of pads controlled by an OE> 20 (per
<Total number of bidirectional pads> – <Total number of pads from the
smallest group of pads controlled by an OE> 15 (per
Table
4–8.
Formula
Altera Corporation
VREF
VREF
June 2006
pad)
pad).