EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 663
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
July 2005
Timing
XGMII signals must meet the timing requirements shown in
Make all XGMII timing measurements at the driver output (shown in
Figure
specified relative to the V
Figure 8–14. XGMII Timing Diagram
Table 8–8
Stratix and Stratix GX devices support DDR data with clock rates of up to
200 MHz, well above the XGMII clock rate of 156.25 MHz. For the HSTL
Class I I/O standard, Stratix and Stratix GX device I/O drivers provide a
1.0-V/ns slew rate at the input buffer of the receiving device.
XAUI
XAUI (pronounced Zowie) is located between the XGMII at the
reconciliation sublayer and the XGMII at the PHY layer.
shows the location of XAUI. XAUI is designed to either extend or replace
XGMII in chip-to-chip applications of most Ethernet MAC to PHY
interconnects.
Note to
(1)
T
T
Table 8–8. XGMII Timing Specifications
setup
hold
RXC, RXD
TXC, TXD,
RX_CLK
The actual set-up and hold times will be made available after device
characterization is complete.
TX_CLK
Symbol
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
8–14) and a capacitive load from all sources of 20 pF that are
Table
shows the XGMII timing specifications.
t
setup
8–8:
Driver
IL
960
960
_AC(max) and V
t
hold
Note (1)
Stratix Device Handbook, Volume 2
t
setup
Receiver
480
480
IH
_AC(min) thresholds.
Figure 8–15
t
hold
V
V
Figure
V
V
IL
IH
IL
IH
_AC(max)
Unit
_AC(max)
_AC(min)
_AC(min)
ps
ps
8–14.
8–19
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