EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 455
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
June 2006
Programmable Current Drive Strength
The Stratix and Stratix GX device I/O pins support various output
current drive settings as shown in
strength settings help decrease the effects of simultaneously switching
outputs (SSO) in conjunction with reducing system noise. The supported
settings ensure that the device driver meets the I
for the corresponding I/O standard.
These drive-strength settings are programmable on a per-pin basis (for
output and bidirectional pins only) using the Quartus II software. To
modify the current strength of a particular pin, see
Strength Settings” on page
Stratix devices support hot socketing without any external components.
In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power-down. Stratix and Stratix GX devices
support any power-up or power-down sequence (V
simplify designs. For mixed-voltage environments, you can drive signals
into the device before or during power-up or power-down without
damaging the device. Stratix and Stratix GX devices do not drive out until
the device is configured and has attained proper operating conditions.
Even though you can power up or down the V
supplies in any sequence you should not power down any I/O bank(s)
that contains the configuration pins while leaving other I/O banks
powered on. For power up and power down, all supplies (V
V
another. This prevents I/O pins from driving out.
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Table 4–7. Programmable Drive Strength
CCIO
This is the Quartus II software default current setting.
I/O banks 1, 2, 5, and 6 do not support this setting.
power planes) must be powered up and down within 100 ms of one
I/O Standard
Table
4–7:
Selectable I/O Standards in Stratix & Stratix GX Devices
4–40.
24 (1), 16, 12, 8, 4
24 (2), 12 (1), 8, 4, 2
16 (1), 12, 8, 2
12 (1), 8, 2
8 (1), 4, 2
I
OH
Table
/ I
OL
Stratix Device Handbook, Volume 2
Current Strength Setting (mA)
4–7. These programmable drive
CCIO
OH
“Programmable Drive
and I
and V
CCIO
OL
and V
CCINT
specifications
CCINT
CCINT
power
and all
) to
4–27
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