EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 586
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Finite Impulse Response (FIR) Filters
Figure 7–3. Hardware View of a DSP Block in Four-Multipliers Adder Mode
Notes to
(1)
(2)
(3)
7–8
Stratix Device Handbook, Volume 2
Coefficients
Coefficients
Coefficients
Coefficients
Data from row
interface block
Data from row
interface block
Data from row
interface block
Data from
interface
interface
from row
interface
interface
interface
from row
from row
from row
block
block
block
block
block
The input registers feed the multiplier blocks. These registers can increase the DSP block performance, but are
optional. These registers can also function as shift registers if the dedicated shiftin/shiftout signals are used.
The pipeline registers are fed by the multiplier blocks. These registers can increase the DSP block performance, but
are optional.
The output registers register the DSP block output. These registers can increase the DSP block performance, but are
optional.
row
input from
Figure
previous
shiftout
block
18
18
18
18
18
18
18
18
7–3:
CLK2
CLR2
D
D
D
D
next block
input to
Q
Q
Q
Q
shiftin
input from
previous
shiftout
block
CLK1
CLR1
D
D
D
D
Q
Q
Q
Q
next block
input to
shiftin
x(n-1)
x(n-2)
x(n-3)
x(n)
h(0)
h(1)
h(2)
h(3)
18
18
18
18
18
18
18
18
Multiplier C
Multiplier D
Multiplier A
Multiplier B
36
36
36
36
D
D
D
D
Q
Q
Q
Q
Notes
37
37
(1). (2),
Altera Corporation
(3)
September 2004
38
D
Q
Output
38
y(n)
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