EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 420
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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DDR Memory Support Overview
Figure 3–13. DQS Configuration in Stratix & Stratix GX IOE
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
3–24
Stratix Device Handbook, Volume 2
You can use the altdqs megafunction to generate the DQS signals.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OE register A
The select line can be chosen in the altdqs MegaWizard Plug-In Manager.
The datain_l and datain_h pins are usually connected to V
DQS postamble handling is not shown in this diagram. For more information, see AN 342: Interfacing DDR SDRAM
with Stratix & Stratix GX Devices.
This undelayed DQS signal goes to the LE for the soft postamble circuitry.
You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.
DQS phase-shift circuitry is only available on DQS pins.
Logic Array
Figure
3–13:
datain_h (3)
(3)
datain_l (4)
system clock
OE
undelayed DQS (6)
combout (7)
OE
during compilation.
(2)
Output Register A
Output Register B
OE Register A
OE Register B
DFF
DFF
DFF
DFF
D
D
D
D
Q
Q
Q
Q
OE
OE
O
O
1
0
CC
Note (1)
and ground, respectively.
0
1
OR2
Shift Circuitry
DQS Phase
(8)
TRI
Altera Corporation
June 2006
DQS Pin (5)
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