EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 703
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
July 2005
Number of PLLs
Minimum input frequency
Maximum input frequency
Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 1 of 2)
Feature
The dedicated clock pins in Stratix and Stratix GX devices can feed the
PLL clock inputs, the global clock networks, and the regional clock
networks. PLL outputs and internally-generated signals can also drive
the global clock network. These global clocks are available throughout
the entire device to clock all device resources.
Stratix and Stratix GX devices are divided into four quadrants, each
equipped with four regional clock networks. The regional clock network
can be fed by either the dedicated clock pins or the PLL outputs within its
device quadrant. The regional clock network can only feed device
resources within its particular device quadrant.
Each Stratix and Stratix GX device provides eight dedicated fast clock
I/O pins FCLK[7..0] versus four dedicated fast I/O pins in APEX II
and APEX 20K devices. The fast regional clock network can be fed by
these dedicated FCLK[7..0] pins or by the I/O interconnect. The I/O
interconnect allows internal logic or any I/O pin to drive the fast regional
clock network. The fast regional clock network is available for general-
purpose clocking as well as high fan-out control signals such as clear,
preset, enable, TRDY and IRDY for PCI applications, or bidirectional or
output pins.
EP1S25 and smaller devices have eight fast regional clock networks, two
per device quadrant. The quadrants in EP1S30 and larger devices are
divided in half, and each half-quadrant can be clocked by one of the eight
fast regional networks. Additionally, each fast regional clock network can
drive its neighboring half-quadrant (within the same device quadrant).
PLLs
Table 10–6
existing APEX II, APEX 20KE and APEX 20KC PLL features.
Two (EP1S30 and
smaller devices);
four (EP1S40 and
larger devices)
3 MHz
250 to 582 MHz
Enhanced PLLs
Stratix & Stratix GX
highlights Stratix and Stratix GX PLL enhancements to
(9)
(2)
Transitioning APEX Designs to Stratix & Stratix GX Devices
Four (EP1S25 and
smaller devices);
eight (EP1S30
and larger
devices)
15 MHz
644.5 MHz
Fast PLLs
(10)
(11)
Four general-
purpose PLLs and
four LVDS PLLs
1.5 MHz
420 MHz
Stratix Device Handbook, Volume 2
APEX II PLLs
Up to four general-
purpose PLLs. Up
to two LVDS PLLs.
(1)
1.5 MHz
420 MHz
APEX 20KC PLLs
APEX 20KE &
10–19
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