EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 674
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 674 of 864
- Download datasheet (11Mb)
Introduction
9–4
Stratix Device Handbook, Volume 2
Figure 9–3. SFI-4 Interface Signals
The framer transmits outbound data via TXDATA[15..0] and is
received at the SERDES using TXCLK. TXCLK is derived from
TXCLK_SRC, which is provided by the OC-192 SERDES. The framer
receives incoming data on RXDATA[15..0] from the OC-192 SERDES.
The data received is latched on the rising edge of RXCLK.
provides the data rates and clock frequencies specified by SFI-4. The
modes of TXCLK are specified by the SFI-4 standard. In required mode
(622 MHz clock mode or 1 mode), TXCLK should run at 622.08 MHz. In
optional mode (311 MHz clock mode or 2 mode), TXCLK should run at
311.04 MHz.
TXDATA[15..0]
TXCLK
TXCLK_SRC
RXDATA[15..0]
RXCLK
REFCLK
Table 9–1. SFI-4 Interface Data Rates & Clock Frequencies
SONET Framer
SONET Framer
Transmitter
Receiver
Signal
TXDATA[15..0]
RXDATA[15..0]
TXCLK_SRC
RXCLK
TXCLK
622.08 Mbps
622.08 MHz or 311.04 MHz
622.08 MHz
622.08 Mbps
622.08 MHz
622.08 MHz
REFCLK
Performance
OC-192 SERDES
Recovered Clock
Transmitter
Receiver
Altera Corporation
Table 9–1
July 2005
Related parts for EP1S20F780I6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: