EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 611
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 611 of 864
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Figure 7–19. 2-Tap 18-Bit Complex FIR Filter Implementation
Altera Corporation
September 2004
x
x
x
h
h
x
h
h
imag1
imag2
real1
real2
real1
imag1
real2
imag2
f
DSP block
DSP block
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
For more information on the different modes of the DSP blocks, see the
DSP Blocks in Stratix & Stratix GX Devices chapter.
Figure 7–19
18-bit inputs. The real and the complex outputs of the DSP blocks are
added externally to generate the overall real and imaginary output. As in
the case of basic, TDM, or polyphase FIR filters, the coefficients may be
loaded in series or parallel.
out
out
out
out
Configured as a subtractor
Configured as a subtractor
Configured as a adder
Configured as a adder
imag1
imag2
real1
real2
shows an example of a 2-tap complex FIR filter design with
= x
= x
= x
= x
real1 *
real2 *
real1 *
real2 *
h
h
h
h
imag1
imag2
real1
real2
- x
- x
+ x
+ x
imag1 *
imag2 *
imag1 *
imag2 *
h
h
h
h
imag1
imag2
real1
real2
Stratix Device Handbook, Volume 2
Overall imaginary output
Overall real output
7–33
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