EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 562
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 562 of 864
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Architecture
6–12
Stratix Device Handbook, Volume 2
1
Routing Structure & Control Signals
This section describes the interface between the DSP blocks and the row
interface blocks. It also describes how the DSP block generates control
signals and how the signals route from the row interface to the DSP block.
DSP Block Interface
The DSP blocks are organized in columns, which provides efficient
horizontal communication between the blocks and the column-based
memory blocks. The DSP block communicates with other parts of the
device through an input and output interface. Each DSP block, including
the input and output interface, is 8 logic array blocks (LABs) long.
The DSP block and row interface blocks consist of eight blocks that
connect to eight adjacent LAB rows on the left and right. Each of the eight
blocks has two regions: right and left, one per row. The DSP block
receives 144 data input signals and 18 control signals for a total of
162 input signals. This block drives out 144 data output signals; 2 of the
data signals can be used as overflow signals (overflow).
provides an overview of the DSP block and its interface to adjacent LABs.
Figure 6–6. DSP Block Interface to Adjacent LABs
Input Interface
The DSP block input interface has 162 input signals from adjacent LABs;
18 data signals per row and 18 control signals per block.
Output Interface
The DSP block output interface drives 144 outputs to adjacent LABs, 18
signals per row from 8 rows.
The output registers form part of the accumulator in the
multiply-accumulate mode.
8 LAB
Rows
Input Interface
DSP Block
162
DSP Block & Row Interface
0 through 7
Interfaces
Row
Control
144
Data
18
Block
DSP
Output Interface
DSP Block
144
8 LAB
Rows
Altera Corporation
Figure 6–6
July 2005
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