EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 566
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Architecture
6–16
Stratix Device Handbook, Volume 2
The DSP block interface generates the clock signals from LAB row clocks
or the local interconnect. The clear signals are generated from the local
interconnects within each DSP block row interface or from LAB row
clocks. The four clock enable signals are generated from the 30 local
interconnects from the same LAB rows that generate the clock signals.
The clock enable is paired with the clock because the enable logic is
implemented at the interface.
within the row interface block.
Figure 6–9. DSP Block Row Interface Signal Distribution
18-Bit Data Routed
from 30 Local
Interconnects
Four Clock Enable
Signals Routed from
30 Local Interconnects
Four Clear Signals
Routed from 30 Local
Interconnects or LAB
Row Clock
Four Clock Signals
Routed from LAB
Row Clock or Local
Interconnect
data[17..0]
Row 1
Row 2
Row 7
Row 8
ena[3..0]
18
Figure 6–9
4
aclr[3..0]
4
clock[3..0]
4
shows the signal distribution
18
18
18
18
Registers
Input
18
18
Altera Corporation
18
18
A1
B1
A4
B4
Multiplier
Multiplier
18 × 18
18 × 18
July 2005
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