EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 331

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 1–10. High-Bandwidth PLL Lock Time
Altera Corporation
July 2005
Frequency (MHz)
160
155
150
145
140
135
130
125
120
0
0.5
A high-bandwidth PLL may benefit a system with two cascaded PLLs. If
the first PLL uses spread spectrum (as user-induced jitter), the second
PLL needs a high bandwidth so it can track the jitter that is feeding it. A
low-bandwidth PLL may, in this case, lose lock due to the spread
spectrum-induced jitter on the input clock.
A low-bandwidth PLL may benefit a system using clock switchover.
When the clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL would react more slowly to changes to its input
clock and take longer to drift to a lower frequency (caused by the input
stopping) than a high-bandwidth PLL.
demonstrate this property.
The two plots show the effects of clock switchover with a low- or high-
bandwidth PLL. When the clock switchover happens, the output of the
low-bandwidth PLL (see
slower than the high-bandwidth PLL output (see
1.0
1.5
2.0
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure
Time (μs)
2.5
1–11) drifts to lower frequency much
3.0
Stratix Device Handbook, Volume 2
Figures 1–11
3.5
Lock Time = 4 μs
Figures
and
4.0
1–12
1–12).
4.5
1–21
5.0