EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 490
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 490 of 864
- Download datasheet (11Mb)
Differential I/O Interface & Fast PLLs
5–18
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
ENA
FPLL7CLK
FPLL8CLK
FPLL9CLK
FPLL10CLK
Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables
Input Pin
PLLs 5, 6, 11, and 12 are not fast PLLs.
Clock pins CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination.
Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for
general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode.
(2)
(2)
(2)
(2)
Table
5–3:
PLL 1
v
v
v
Clock Input & Fast PLL Output Relationship
Table 5–3
signal (ENA).
connect to across all Stratix family devices.
All Stratix Devices
PLL 2
v
v
v
summarizes the PLL interface to the input clocks and the enable
PLL 3
Table 5–4
v
v
v
PLL 4
summarizes the clock networks each fast PLL can
v
v
v
PLL 7
v
v
v
(3)
EP1S30 to EP1S80 Devices Only
Note (1)
PLL 8
v
v
v
(3)
v
PLL 9
Altera Corporation
(3)
v
v
v
July 2005
PLL 10
(3)
v
v
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