EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 344
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Fast PLLs
1–34
Stratix Device Handbook, Volume 2
Clock Multiplication & Division
Stratix and Stratix GX device fast PLLs provide clock synthesis for PLL
output ports using m/(post scaler) scaling factors. The input clock is
multiplied by the m feedback factor. Each output port has a unique post
scale counter to divide down the high-frequency VCO. There is one
multiply counter, m, per fast PLL with a range of 1 to 32. There are three
post-scale counters (g0, l0, and l1) for the regional and global clock output
ports. All post-scale counters range from 1 to 32. If the design uses a
high-speed serial interface, you can set the output counter to 1 to allow
the high-speed VCO frequency to drive the SERDES.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-
synchronous transmitters or for general-purpose external clocks. There
are no dedicated external clock output pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank. See the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device
Handbook, Volume 2 for output standard support.
Table 1–12
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
PCML
LVDS
HyperTransport technology
Differential HSTL
Table 1–12. Fast PLL Port I/O Standards (Part 1 of 2)
shows the I/O standards supported by fast PLL input pins.
I/O Standard
INCLK
v
v
v
v
v
v
v
v
v
v
Input
Altera Corporation
PLLENABLE
v
v
July 2005
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