EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 564
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Architecture
Figure 6–7. DSP Row Interface Block
6–14
Stratix Device Handbook, Volume 2
C4 and C8
Interconnects
LAB
DSP Block to
LAB Row Interface
Block Interconnect Region
DirectLink Interconnect
from Adjacent LAB
10
Control Signals in the Row Interface Block
The DSP block has a set of input registers, a pipeline register, and an
output register. Each register is grouped in banks that share the same
clock and clear resources:
■
■
■
1- to 9-bit banks for the input register
1- to 18-bit banks for the pipeline register
18 bits for the output register
Row Interface
3
18
Block
18 Inputs per Row
R4 and R8 Interconnects
10
9
Control
[17..0]
DSP Block
Row Structure
[17..0]
18 Outputs per Row
Nine DirectLink Outputs
to Adjacent LABs
18
18
9
Altera Corporation
DirectLink Interconnect
from Adjacent LAB
July 2005
LAB
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