EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 473
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Introduction
Stratix I/O Banks
Altera Corporation
July 2005
S52005-3.2
To achieve high data transfer rates, Stratix devices support True-
LVDS
serializer/deserializer (SERDES) circuitry for each differential I/O pair.
Stratix SERDES circuitry transmits and receives up to 840 megabits per
second (Mbps) per channel. The differential I/O interfaces in Stratix
devices support many high-speed I/O standards, such as LVDS,
LVPECL, PCML, and HyperTransport
speed modules are designed to provide solutions for many leading
protocols such as SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO,
HyperTransport technology, and UTOPIA-4.
The SERDES transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide
words and transmit them across either a cable or printed circuit board
(PCB). The SERDES receiver takes the serialized data and reconstructs the
bits into a 4-, 7-, 8-, or 10-bit-wide parallel word. The SERDES contains the
necessary high-frequency circuitry, multiplexer, demultiplexer, clock,
and data manipulation circuitry. You can use double data rate I/O
(DDRIO) circuitry to transmit or receive differential data in by-one (
or by-two (
1
This chapter describes the high-speed differential I/O capabilities of
Stratix programmable logic devices (PLDs) and provides guidelines for
their optimal use. You should use this document in conjunction with the
Stratix Device Family Data Sheet section of the Stratix Device Handbook,
Volume 1. Consideration of the critical issues of controlled impedance of
traces and connectors, differential routing, termination techniques, and
DC balance gets the best performance from the device. Therefore, an
elementary knowledge of high-speed clock-forwarding techniques is also
helpful.
Stratix devices contain eight I/O banks, as shown in
I/O banks on each side contain circuitry to support high-speed LVDS,
LVPECL, PCML, HSTL Class I and II, SSTL-2 Class I and II, and
HyperTransport inputs and outputs.
TM
differential I/O interfaces which have dedicated
Contact Altera Applications for more information on other B
values that the Stratix devices support and using
Quartus
B = 1 and B = 7 in
×
2) modes.
5. High-Speed Differential I/O
®
Interfaces in Stratix Devices
II software. Stratix devices currently only support
×
7 mode.
TM
technology. Stratix device high-
Figure
×
7-mode in the
5–1. The two
×
5–1
1)
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