EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 752
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Configuration Schemes
Figure 11–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
11–34
Stratix Device Handbook, Volume 2
CONF_DONE
Upon power-up, nSTATUS is held low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or
Stratix GX device.
Device I/O pins are in user mode.
RDYnBSY
nSTATUS
Figure
DATA[7..0]
INIT_DONE
nCONFIG
nWS
nCS
User I/Os
CS
(
(
(
(
(
(
11–18:
1)
2)
3)
3)
3)
3)
t
t
CF2CD
t
CF2ST0
CFG
t
STATUS
t
CF2ST1
PPA Configuration Timing
Figure 11–18
for PPA configuration.
t
CF2WS
High-Z
t
CSSU
t
DSU
Byte 0
t
DH
shows the Stratix and Stratix GX device timing waveforms
t
WS2B
t
WSP
Byte 1
t
RDY2WS
Byte n Ð 1
t
CSSU
t
CSH
t
BUSY
Byte n
Altera Corporation
t
July 2005
CD2UM
(
(
(
(
(
4)
4)
4)
4)
4)
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