EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 427
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 427 of 864
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Altera Corporation
Chapter
5
September 2004,
November 2003,
April 2004, v3.0
July 2005, v3.2
July 2003, v2.0
October 2003,
Date/Version
v3.1
v2.2
v2.1
Updated
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Updated Note 3 in
Updated
Updated
Updated description of
page
Updated Note 5 in
Updated Notes 2, 5, and 7 in
through
Added new text about spanning two I/O banks on
page
Updated notes for
Updated
“Data Alignment with Clock”
made from 90 degrees to 180 degrees.
Removed support for series and parallel on-chip
termination.
Updated the number of channels per PLL in Tables 5-10
through 5-14.
Added -8 speed grade device information, including Tables
5-7 and 5-8.
Format changes throughout Chapter.
Relaxed restriction of input pins next to differential pins for
flip chip packages in Figure 5-1, Note 5.
Wire bond package performance specification for “high”
speed channels was increased to 624 Mbps from 462 Mbps
throughout Chapter.
Updated high-speed I/O specification for J=2 in Tables 5-7
and 5-8.
Updated Tables 5-10 to 5-14 to reflect PLL cross-bank
support for high-speed differential channels at full speed.
Increased maximum output clock frequency to 462 to 500
MHz on page 5-66.
5–46.
5–60.
Table 5–14 on page
Table 5–14 on page
Table 5–7 on page
Table 5–8 on page
Table
5–7, 5–8, and 5–10.
Figure
Table 5–10 on page
Table 5–14 on page
Changes Made
“R
5–17.
D
5–58.
Differential Termination” on
section, last sentence: change
5–34.
5–36.
5–58.
Table 5–11 on page 5–56
5–54.
5–58.
Comments
I/O Standards
Section III–3
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