EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 607
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 607 of 864
- Download datasheet (11Mb)
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Polyphase Decimation Filter Implementation
Figure 7–17
Figure 7–16
coefficients of the polyphase filters need to be cycled using the schedule
shown in
Table 7–13. Coefficient Loading Schedule for Polyphase Decimation Filter
(D=4)
Cycle of 4 Clock
1, 5,...
2, 6,...
3, 7,...
4, 8,...
Table
shows the decimation polyphase filter example of
as it would fit into Stratix or Stratix GX DSP blocks. The
7–13. The output y(n), is clocked using the 1 clock.
h(3), h(7), h(11), h(15)
h(2), h(6), h(10), h(14)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
Coefficients to Load
Stratix Device Handbook, Volume 2
Corresponding RAM/ROM
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
7–29
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