EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 744
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Configuration Schemes
11–26
Stratix Device Handbook, Volume 2
default, the INIT_DONE output is disabled. You can enable the
INIT_DONE output by turning on the Enable INIT_DONE output
option in the Quartus II software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for maximum value of
t
the device has been initialized properly and that it has entered user mode.
During configuration and initialization and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
If the Stratix or Stratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The pin on the
microprocessor connected to nSTATUS must be an input. The
microprocessor can then pulse nCONFIG low to restart the configuration
error. With the Auto-restart configuration after error option on, the
Stratix or Stratix GX device releases nSTATUS after a reset time-out
period. After nSTATUS is released, the microprocessor can reconfigure
the Stratix or Stratix GX device without pulsing nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
the data and the initialization clock starts but CONF_DONE and
INIT_DONE have not gone high, it must reconfigure the Stratix or
Stratix GX device. After waiting the specified 136 DCLK cycles, the
microprocessor should restart configuration by pulsing nCONFIG low.
Figure 11–12
configuration using a microprocessor.
CD2UM
(see
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 40 µs).
Table
shows the circuit for Stratix and Stratix GX parallel
11–9) after the CONF_DONE signal goes high to ensure
Altera Corporation
July 2005
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