EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 492

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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0
Differential I/O Interface & Fast PLLs
5–20
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
DIFFIOCLK14
DIFFIOCLK15
DIFFIOCLK16
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2)
Output Signal
PLLs 5, 6, 11, and 12 are not fast PLLs.
The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be
driven by a dedicated clock pin (CLK[3..0] and CLK[8..11]) or the corner pins that clock the corner PLLs
(FPLL[10..7]CLK).
Table
5–4:
PLL 1
Fast PLL Specifications
You can drive the fast PLLs by an external pin or any one of the sectional
clocks [21..0]. You can connect the clock input directly to local or global
clock lines, as shown in
inputs to the fast PLL’s input multiplexer for the receiver PLL. You can
only use the sectional clock inputs in the transmitter only mode or as a
general purpose PLL.
All Stratix Devices
PLL 2
PLL 3
PLL 4
Figure
5–14. You cannot use the sectional-clock
PLL 7
EP1S30 to EP1S80 Devices Only
Notes
PLL 8
(1),
(2)
PLL 9
Altera Corporation
v
July 2005
PLL 10
v
v

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