EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 480
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Principles of SERDES Operation
Figure 5–3. Stratix High-Speed Interface Deserialized in
Notes to
(1)
(2)
Figure 5–4. Receiver Timing Diagram
5–8
Stratix Device Handbook, Volume 2
RXCLKIN+
RXCLKIN−
W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10.
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
This figure does not show additional circuitry for clock or data manipulation.
Internal ×10 clock
Internal ×10 clock
Internal ×1 clock
Internal ×1 clock
RXIN+
RXIN−
Figure
RXLOADEN
RXLOADEN
data input
data input
Receiver
Receiver
5–3:
Receiver Circuit
n – 1
n – 1
PLL (2)
Fast
Serial Shift
Registers
n – 0
n – 0
RXLOADEN
TXLOADEN
× W
9
9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
8
8
Registers
Parallel
7
7
×
10 Mode
6
6
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
× W / J (1)
5
5
Registers
Parallel
4
4
3
3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
2
2
Altera Corporation
1
1
Logic Array
Stratix
0
0
July 2005
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