EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 515
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 515 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
SERDES Bypass DDR Differential Signaling Receiver Operation
The SERDES bypass differential signaling receiver uses the Stratix device
DDR input circuitry to receive high-speed serial data. The DDR input
circuitry consists of a pair of shift registers used to capture the high-speed
serial data, and a latch.
One register captures the data on the positive edge of the clock (generated
by PLL) and the other register captures the data on the negative edge of
the clock. Because the data captured on the negative edge is delayed by
one-half of the clock cycle, it is latched before it interfaces with the system
logic.
Figure 5–28
serial data and the clock. In this example, the inclock signal is running
at half the speed of the incoming data. However, other combinations are
also possible.
used in a Flexible-LVDS receiver design to interface with the system logic.
Figure 5–28.
neg_reg_out
dataout_h
dataout_l
datain
clock
shows the DDR timing relationship between the incoming
×
Figure 5–29
2 Timing Relation between Incoming Serial Data & Clock
XX
B0
XX
XX
High-Speed Differential I/O Interfaces in Stratix Devices
A0
shows the DDR input and the other modules
B0
B1
B0
A0
A1
Stratix Device Handbook, Volume 2
B1
B2
B1
A1
A2
B2
B3
B2
A2
A3
B3
5–43
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