EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 99
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 99 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
Figure 2–42. Global Clocking
Note to
(1)
Regional Clock Network
There are four regional clock networks within each quadrant of the Stratix
device that are driven by the same dedicated CLK[15..0] input pins or
from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the
top left quadrant, RCLK[8..11] are in the top-right quadrant,
RCLK[4..7] are in the bottom-left quadrant, and RCLK[12..15] are in
the bottom-right quadrant. The regional clock networks only pertain to
the quadrant they drive into. The regional clock networks provide the
lowest clock delay and skew for logic contained within a single quadrant.
RCLK cannot be driven by internal logic. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in
from PLLs and CLK pins.
CLK[3..0]
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input to the fast PLL can be driven by an
output from another PLL, a pin-driven global or regional clock, or internally-
generated global signals.
Figure
Figure
2–42:
Global Clock [15..0]
2–43. See
CLK[7..4]
Figures 2–50
Note (1)
CLK[15..12]
Stratix Device Handbook, Volume 1
Global Clock [15..0]
and
2–51
for RCLK connections
Stratix Architecture
CLK[11..8]
2–75
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