ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 121

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

16.7.1
16.7.2
16.7.3
9223B–AVR–09/11
Force Output Compare
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x
Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-
put glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is
disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Com-
pare) Register is only changed by a write operation (the Timer/Counter does not update this
register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the
high byte temporary register (TEMP). However, it is a good practice to read the low byte first
as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the
TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH)
has to be written first. When the high byte I/O location is written by the CPU, the TEMP Regis-
ter will be updated by the value written. Then when the low byte (OCR1xL) is written to the
lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or
OCR1x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to
on page
In non-PWM Waveform Generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set
the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real com-
pare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set,
cleared or toggled).
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized
to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT1 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT1 when using any of the Output
Compare channels, independent of whether the Timer/Counter is running or not. If the value
written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will con-
tinue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter
is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-
pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
changing between Waveform Generation modes.
Atmel ATmega48PA/88PA/168PA [Preliminary]
113.
“Accessing 16-bit Registers”
121