ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 310

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

28.8.1
28.8.2
310
Atmel ATmega48PA/88PA/168PA [Preliminary]
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 28-17. Pin Mapping Serial Programming
When writing serial data to the Atmel
ing edge of SCK.
When reading data from the Atmel ATmega48PA/88PA/168PA, data is clocked on the falling
edge of SCK. See
To program and verify the Atmel ATmega48PA/88PA/168PA in the serial programming mode,
the following sequence is recommended (See Serial Programming Instruction set in
28-19 on page
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte
Apply power between V
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
at a time by supplying the 6 LSB of the address and data together with the Load Pro-
gram Memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram Memory Page is stored by loading the Write Program Memory Page instruction
with the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at
least t
programming interface before the Flash write operation completes can result in incor-
rect programming.
Symbol
MOSI
MISO
SCK
WD_FLASH
312):
Figure 28-9
before issuing the next page (See
Pins
PB3
PB4
PB5
CC
for timing details.
and GND while RESET and SCK are set to “0”. In some
®
ATmega48PA/88PA/168PA, data is clocked on the ris-
I/O
O
I
I
Table
28-18). Accessing the serial
Serial Data out
Serial Data in
Description
Serial Clock
9223B–AVR–09/11
Table