ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 210

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

21.8.4
210
Atmel ATmega48PA/88PA/168PA [Preliminary]
UCSRnC – USART MSPIM Control and Status Register n C
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete inter-
rupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is
written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will over-
ride normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)
has no meaning since it is the transmitter that controls the transfer clock and since only master
mode is supported.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn
to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnB is written.
• Bit 7:6 – UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
– USART Control and Status Register n C” on page 199
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is
enabled.
Table 21-4.
Bit
Read/Write
Initial Value
UMSELn1
0
0
1
1
UMSELn1
UMSELn Bits Settings
R/W
7
0
UMSELn0
R/W
6
0
UMSELn0
1
0
1
0
R
5
–
0
R
4
–
0
Mode
Asynchronous USART
Reserved
Master SPI (MSPIM)
Synchronous USART
R
3
–
0
UDORDn
R/W
2
1
for full description of the normal
UCPHAn
Table
R/W
1
1
21-4. See
UCPOLn
R/W
0
0
9223B–AVR–09/11
“UCSRnC
UCSRnC