ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 275

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

26.3
26.3.1
9223B–AVR–09/11
Register Description
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to
control the Program memory operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during
EEPROM write or SPM.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as
zero in Atmel
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see
the Signature Row from Software” on page 286
cycles
after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use
and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in Atmel ATmega48PA is a subset of the functionality in the Atmel
ATmega48PA/88PA/168PA. If the RWWSRE bit is written while filling the temporary page buf-
fer, the temporary page buffer will be cleared and the data will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in Atmel ATmega48PA is a subset of the functionality in the Atmel
ATmega48PA/88PA/168PA. An LPM instruction within three cycles after BLBSET and SELF-
PRGEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits
(depending on Z0 in the Z-pointer) into the destination register. See
Lock Bits from Software” on page 271
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is exe-
cuted within four clock cycles. The CPU is halted during the entire Page Write operation.
Bit
0x37 (0x57)
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
®
SPMIE
ATmega48PA.
R/W
7
0
RWWSB
R
6
0
SIGRD
R/W
5
0
for details.
RWWSRE
R/W
4
0
for details. An SPM instruction within four
BLBSET
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
“Reading the Fuse and
SELFPRGEN
R/W
0
0
“Reading
SPMCSR
275
®