ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 56

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

11.9.2
56
Atmel ATmega48PA/88PA/168PA [Preliminary]
WDTCSR – Watchdog Timer Control Register
• Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt
is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-
rupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer
occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode.
The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt
vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System
Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt.
To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This
should however not be done within the interrupt service routine itself, as this might compro-
mise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed
before the next time-out, a System Reset will be applied.
Table 11-1.
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during
conditions causing failure, and a safe start-up after the failure.
Note:
Bit
(0x60)
Read/Write
Initial Value
WDTON
1
1
1
1
0
1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.
(1)
Watchdog Timer Configuration
WDIF
R/W
WDE
7
0
0
0
1
1
x
WDIE
R/W
6
0
WDIE
0
1
0
1
x
WDP3
R/W
5
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
WDE
R/W
X
3
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
WDP0
R/W
0
0
9223B–AVR–09/11
WDTCSR