ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 178

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20.3.1
178
Atmel ATmega48PA/88PA/168PA [Preliminary]
Internal Clock Generation – The Baud Rate Generator
Figure 20-2
Figure 20-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
when the UBRRnL Register is written. A clock is generated each time the counter reaches
zero. This clock is the baud rate generator clock output (= f
divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate
generator output is used directly by the Receiver’s clock and data recovery units. However,
the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by
the state of the UMSELn, U2Xn and DDR_XCKn bits.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or
txclk
rxclk
xcki
xcko
fosc
DDR_XCKn
XCKn
Pin
shows a block diagram of the clock generation logic.
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRRn
Sync
UBRRn+1
foscn
Detector
UCPOLn
Edge
/2
Figure
/4
20-2.
osc
/2
/(UBRRn+1)). The Transmitter
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
9223B–AVR–09/11
UMSELn
txclk
rxclk