ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 144

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

18.2.1
18.2.2
18.3
144
Timer/Counter Clock Sources
Atmel ATmega48PA/88PA/168PA [Preliminary]
Registers
Definitions
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit
registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt
Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask
Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked
from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is con-
trolled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls
which clock source he Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pins
(OC2A and OC2B). See
event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an
Output Compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT2 for accessing
Timer/Counter2 counter value and so on.
The definitions in
Table 18-1.
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the
Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous
operation, see
sources and prescaler, see
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value
stored in the OCR2A Register. The assignment is dependent on the mode of operation.
Definitions
“ASSR – Asynchronous Status Register” on page
Table 18-1
“Output Compare Unit” on page 146
“Timer/Counter Prescaler” on page
are also used extensively throughout the section.
T2
is by default equal to the MCU clock, clk
T2
).
for details. The compare match
157.
164. For details on clock
9223B–AVR–09/11
I/O
. When the