ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 199

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20.11.4
9223B–AVR–09/11
UCSRnC – USART Control and Status Register n C
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with
nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in
Table 20-8.
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn set-
ting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 20-9.
Note:
Bit
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
UMSELn1
UPMn1
1. See
0
0
1
1
0
0
1
1
(MSPIM) operation
UMSELn1
UMSELn Bits Settings
UPMn Bits Settings
R/W
7
0
“USART in SPI Mode” on page 202
UMSELn0
R/W
6
0
UMSELn0
UPMn0
0
1
0
1
0
1
0
1
UPMn1
R/W
5
0
UPMn0
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
R/W
4
0
for full description of the Master SPI Mode
USBSn
R/W
3
0
UCSZn1
R/W
(1)
2
1
UCSZn0
Table
R/W
1
1
20-8.
UCPOLn
R/W
0
0
UCSRnC
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