ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 198

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20.11.3
198
Atmel ATmega48PA/88PA/168PA [Preliminary]
UCSRnB – USART Control and Status Register n B
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address
information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more
detailed information see
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete inter-
rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete inter-
rupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn
to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Bit
Read/Write
Initial Value
RXCIEn
R/W
7
0
TXCIEn
R/W
“Multi-processor Communication Mode” on page
0
6
UDRIEn
R/W
5
0
RXENn
R/W
4
0
TXENn
R/W
3
0
UCSZn2
R/W
2
0
RXB8n
R
1
0
193.
TXB8n
R/W
0
0
9223B–AVR–09/11
UCSRnB