ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 165

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

18.11.9
9223B–AVR–09/11
GTCCR – General Timer/Counter Control Register
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B,
TCCR2A and TCCR2B the value in the temporary storage register is read.
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchro-
nous mode, the bit will remain one until the prescaler has been reset. The bit will not be
cleared by hardware if the TSM bit is set. Refer to the description of the
Timer/Counter Synchronization Mode” on page 142
Synchronization mode.
Bit
0x23 (0x43)
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
TSM
R/W
7
0
R
6
–
0
R
5
–
0
R
4
–
0
3
–
R
0
for a description of the Timer/Counter
R
2
–
0
PSRASY
R/W
1
0
PSRSYNC
R/W
“Bit 7 – TSM:
0
0
GTCCR
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