ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 180

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20.3.4
20.4
180
Frame Formats
Atmel ATmega48PA/88PA/168PA [Preliminary]
Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock
input (Slave) or clock output (Master). The dependency between the clock edges and data
sampling or data change is the same. The basic principle is that data input (on RxDn) is sam-
pled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 20-3. Synchronous Mode XCKn Timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which
is used for data change. As
changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data
will be changed at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and
stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combina-
tions of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the
parity bit is inserted after the data bits, before the stop bits. When a complete frame is trans-
mitted, it can be directly followed by a new frame, or the communication line can be set to an
idle (high) state.
inside brackets are optional.
Figure 20-4. Frame Formats
UCPOL = 1
UCPOL = 0
(IDLE)
Figure 20-4
RxD / TxD
RxD / TxD
St
XCK
XCK
0
1
illustrates the possible combinations of the frame formats. Bits
Figure 20-3
2
3
4
FRAME
shows, when UCPOLn is zero the data will be
[5]
[6]
[7]
[8]
[P]
Sample
Sample
Sp1 [Sp2]
(St / IDLE)
9223B–AVR–09/11