ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 19

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

8.3.1
8.4
8.4.1
9223B–AVR–09/11
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 8-4.
The Atmel
ory. It is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between
the EEPROM and the CPU is described in the following, specifying the EEPROM Address
Registers, the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 294
ming in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains
instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction
is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the
next instruction is executed.
Atmel ATmega48PA/88PA/168PA [Preliminary]
®
“Preventing EEPROM Corruption” on page 20
CC
ATmega48PA/88PA/168PA contains 256/512/512K bytes of data EEPROM mem-
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Address
clk
Data
Data
WR
CPU
RD
Compute Address
T1
Memory Access Instruction
contains a detailed description on EEPROM Program-
Address valid
T2
CPU
Table
cycles as described in
for details on how to avoid problems
8-2. A self-timing function, however,
Next Instruction
T3
Figure
8-4.
19