ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 150

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

18.7.3
150
Atmel ATmega48PA/88PA/168PA [Preliminary]
Fast PWM Mode
An interrupt can be generated each time the counter value reaches the TOP value by using
the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for
updating the TOP value. However, changing TOP to a value close to BOTTOM when the
counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCR2A is lower
than the current value of TCNT2, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the
compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its log-
ical level on each compare match by setting the Compare Output mode bits to toggle mode
(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of f
f
ing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the
the counter counts from MAX to 0x00.
The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option
by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from
BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In
non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare
match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode,
the output is set on compare match and cleared at BOTTOM. Due to the single-slope opera-
tion, the operating frequency of the fast PWM mode can be twice as high as the phase correct
PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode
well suited for power regulation, rectification, and DAC applications. High frequency allows
physically small sized external components (coils, capacitors), and therefore reduces total
system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent com-
pare matches between OCR2x and TCNT2.
f
clk_I/O
OCnx
/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the follow-
=
------------------------------------------------------- -
2
N
f
clk_I/O
1
+
OCRnx
Figure
18-6. The TCNT2 value is in the timing diagram shown as a
TOV2
Flag is set in the same timer clock cycle that
9223B–AVR–09/11
OC2A
=