ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 220

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

22.5.2
22.5.3
22.5.4
220
Atmel ATmega48PA/88PA/168PA [Preliminary]
Bit Rate Generator Unit
Bus Interface Unit
Address Match Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI
Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings,
but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL fre-
quency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI
bus clock period. The SCL frequency is generated according to the following equation:
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller
and Arbitration detection hardware. The TWDR contains the address or data bytes to be trans-
mitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface
Unit also contains a register containing the (N)ACK bit to be transmitted or received. This
(N)ACK Register is not directly accessible by the application software. However, when receiv-
ing, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in
Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the
TWSR.
The START/STOP Controller is responsible for generation and detection of START,
REPEATED START, and STOP conditions. The START/STOP controller is able to detect
START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling
the MCU to wake up if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has
lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropri-
ate status codes generated.
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in
the TWAR is written to one, all incoming address bits will also be compared against the Gen-
eral Call address. Upon an address match, the Control Unit is informed, allowing correct action
to be taken. The TWI may or may not acknowledge its address, depending on settings in the
TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in
sleep mode, enabling the MCU to wake up if addressed by a Master.
SCL frequency
• TWBR = Value of the TWI Bit Rate Register.
• PrescalerValue = Value of the prescaler, see
Pull-up resistor values should be selected according to the SCL frequency and the capacitive
bus line load. See
=
------------------------------------------------------------------------------------------ -
16
+
2(TWBR)
Table 29-8 on page 321
CPU Clock frequency
PrescalerValue
for value of pull-up resistor.
Table 22-8 on page
242.
9223B–AVR–09/11