ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 173

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

19.5
19.5.1
9223B–AVR–09/11
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the
if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable
SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to
summarized below:
Table 19-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first)
or trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 19-4.
Bit
0x2C (0x4C)
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
CPOL
CPHA
0
1
0
1
CPOL Functionality
CPHA Functionality
SPIE
R/W
7
0
Figure 19-3
SPE
R/W
6
0
DORD
R/W
5
0
and
Figure 19-3
Leading Edge
Leading Edge
Figure 19-4
Sample
MSTR
Falling
Rising
R/W
Setup
4
0
and
CPOL
R/W
for an example. The CPOL functionality is
3
0
Figure 19-4
CPHA
R/W
2
0
for an example. The CPOL
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
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